1. Technical Field
The present invention relates to digital circuits in general, and in particular to latch circuits. Still more particularly, the present invention relates to a latch circuit capable of ensuring race-free staging of signals for dynamic logic circuits.
2. Description of Related Art
When two latch circuits are cascaded in series with few or no logic circuits in between, it is possible for data to race through the first latch circuit and corrupt the data in the second latch circuit. Such race condition can be caused by many reasons. For example, the delay for storing data in the first latch circuit may be too small, the clock signal may reach the second latch circuit relatively late in time, or the hold time for the second latch circuit may be too large. The problem of race condition is particularly prominent for logic circuits in which clocks are intentionally delayed to save power.
There are several known solutions to the race condition problem. The most common solution is to insert a number of buffers (i.e., inverters) or delay elements between the output of the first latch circuit and the input of the second latch circuit. However, it is difficult to ascertain the exact number of buffers or delay elements that need to be inserted. On the one hand, too many buffers or delay elements will waste power and space and may even limit clock frequency; but on the other hand, too few buffers or delay elements will not solve the race condition problem. Another common solution (for edge-triggered logic circuits) is to insert a third latch circuit between the first and the second latch circuits. The third latch circuit is triggered on the opposite edge of the clock to prevent the new data from reaching the second latch circuit until a full phase has lapsed after the clock edge. Unfortunately, such solution places an additional load on the clock distribution network, which may lead to too much power and space being consumed. In essence, none of the known solutions is completely satisfactory. Besides, for all the known solutions, a signal is only delayed enough to prevent race conditions between two consecutive latch circuits. In other words, more buffers, delay elements or latch circuits are required if a signal is to be delayed for more than one cycle.
Consequently, it is desirable to provide an improved latch circuit that is capable of overcoming race conditions within dynamic logic circuits.